`timescale 1ns/1ps module inverter(x, y); input x; output y; assign y = ~x; endmodule module tb_inverter(); reg x; wire y; initial begin $dumpfile("test.vcd"); $dumpvars(1, tb_inverter); #0 x = 0; #100 $finish; end always #10 x = ~x; inverter i1(.x(x), .y(y)); endmodule