module BUF(input X, output Y); assign Y = X; endmodule module INV(input X, output Y); assign Y = ~X; endmodule module NAND2(X1, X2, Y); input X1, X2; output Y; assign Y = ~(X1 & X2); endmodule module NOR2(X1, X2, Y); input X1, X2; output Y; assign Y = ~(X1 | X2); endmodule module DFF(CLK, D, Q, nQ); input CLK, D; output reg Q, nQ; always @(negedge CLK) begin Q <= D; nQ <= ~D; end endmodule module DFFSR(CLK, D, S, R, Q, nQ); input CLK, D, S, R; output reg Q, nQ; always @(posedge R, posedge S, negedge CLK) begin if(S) begin Q <= 1'b1; nQ <= 1'b0; end else if(R) begin Q <= 1'b0; nQ <= 1'b1; end else begin Q <= D; nQ <= ~D; end end endmodule